资源列表
vgaclock.rar
- vga显示的数字时钟,用mif文件实现，用以大家学习交流,vga display digital clock, with the realization of mif file for them to learn from the exchange of
sim.rar
- 通用的循环码编码器和（7,4）循环码译码器。采用VERILOG HDL编写，通过硬件验证。需使用modelsim 5.6仿真,Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6
xapp460.zip
- 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）,Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
xapp622.zip
- 644 MHz SDR LVDS 发射器/接收器(verilog and doc),644-MHz SDR LVDS Transmitter/Receiver
dacconf.rar
- 通信中常用的AD9857芯片的FPGA配置源码VERILOG实现,Communications commonly used in the AD9857 chip FPGA realization of VERILOG source configuration
CY7C68013.rar
- USB2.0的Verilog实现，含有完整的FPGA代码,Use Verilog to implement the USB2.0 protcol
car1.rar
- 基于FPGA控制的红外循迹小车，八个传感器，利用PWM进行控制转弯和前进后退，可以自启动,FPGA-based infrared tracking control car, eight sensors, using PWM to control turning and forward and back, you can self-starting
调幅发射机的设计
- 高频设计，调幅发射机的设计！以及电路模块-High-frequency design, the AM transmitter design! And the circuit module
A/D转换芯片TLC2543的verilog编程
- A/D转换芯片TLC2543的verilog编程，根据TLC5243的datasheet编写，程序简单，结构清晰，可以借鉴应用-A/D converter chip TLC2543 the verilog programming
memristor
- 忆阻器的SPICE建模模型说明及仿真结果说明-Memristor SPICE modeling and simulation results show that the model describes
CAN_IP.rar
- 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。,This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
FPGA.rar
- 关于FPGA查找表内部结构的介绍，对查找表的建立与使用也有初步讲解 ,FPGA lookup table on the internal structure, the look-up table for the establishment and initial on the use of