资源列表
kcu105_sgmii_over_lvds
- sgmii use verilog coding,and can work 1000M ethernet
H.265视频压缩的FPGA实现
- 使用verilog语言实现H.265压缩算法,能够实现实时视频数据的压缩传输(Using Verilog language to realize h.265 compression algorithm can realize the compression and transmission of real-time video data)
STM32F1步进电机S加减速源代码
- stm32单片机控制步进电机,控制步进电机加减速算法(Stepping motor controlled by single chip microcomputer)
basketball_24time1
- 该文档主要是用verilog语言实现篮球24秒计时器,这是我做的数字电子技术课程的一次大作业。 里面为整个文件夹,解压之后可在Quartus13.0上直接运行。(This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technology course I do. It contains the
FPGA实现Jpeg压缩,和视频采集程序
- FPGA实现Jpeg压缩,和视频采集程序(Zynq - Main - register access Mio)
课程设计-数字钟
- 具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)
4乘4键盘扫描控制器
- 1. 键值采用16进制编码,即16个按键分别对应显示16进制数 0~F,按键对应关系如下:最上面一行从左至右依次为0~3, 第二行从左至右依次为4~7,第三行从左至右依次为8~B,最 下面一行从左至右依次为C~F,其中b、d显示为小写,其他字 母大写; 2. 按键按下时显示当前键值并保持,直到下一按键被按下时更新 显示; 3. 只有按键被按下时蜂鸣器发出按键音,放开后蜂鸣器不发声。 4. 每个按键对应不同的按键音。(1. The key value is encoded in hexadecim
CNN
- THU微纳电子系ic设计课程大作业,使用verilog实现CNN加速器,含一层卷积和池化,仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)
1
- 数字通信同步技术的MATLAB与FPGA实现 Altera Verilog版.pdf(Synchronization technology of digital communication MATLAB FPGA Altera Verilog.pdf)
AXI slave
- AXI slave 完整 verilog代码。测试验证通过。
异步FIFO
- 纯Verilog实现的异步FIFO,分为读写控制模块,SRAM CORE,同步等几个模块,内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
spartan6 ddr3 controler
- xilinx spartan6 ddr3 test demo