资源列表
ADS1256
- ads1256驱动代码,用verilog编写,在quartus上运行成功(ADS1256 driver code, written in Verilog, runs successfully on quartus.)
down_up_dds
- 在Vivado下完成AD输入到下变频的功能,频率可配置,通用化设计。(The function of AD input to down conversion is completed under Vivado, and the frequency is configurable and universal design.)
SPI_UART
- SPI读写AD9361,通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)
128点 基8 FFT
- 使用Verilog语言对128点 基8FFT的实现(Implementation of 128-point basis 8FFT)
flashZ
- FPGA控制m25p16flash芯片读写控制spi协议 可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA Erase Write-Read Function)
AD7760_TEST
- AD7760模数转换,使能滤波器功能,简单易懂,可进行各种配置 全功能支持,并附加使用说明(AD7760 Full Function Support with Additional Instructions)
multiplication
- 在FPGA里面实现了多位乘法器的功能,并用modelsim进行了仿真,还对该乘法器进行了优化(The function of multi-bit multiplier is realized in the FPGA, and it is simulated with modelsim, and the multiplier is optimized)
数字信号处理的FPGA实现(第4版)源码
- 数字信号处理的FPGA实现(第4版)的配套源码,极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
master_slave
- AXI4-Lite总线的主从机读写,例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
PID_Verilog
- PID算法用verilog语言实现,实测可用,由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)
哈夫曼编码器设计实验报告
- 要求对一段数据序列进行哈夫曼编码,使得平均码长最短,输出各元素编码和编码后的数据序列。 ①组成序列的元素是[0-9]这10个数字,每个数字其对应的4位二进制数表示。比如5对应0101,9对应1001。 ②输入数据序列的长度为256。 ③先输出每个元素的编码,然后输出数据序列对应的哈夫曼编码序列。(Design a 1MHz FIR low pass filter. Huffman coding is required for a section of data sequence to m
rgb2ycbcr
- rgb to YCbCr converter