资源列表
scoreboard
- MIPS体系结构用verilog实现的记分牌算法，标流水线-Architecture implemented using verilog scoreboard algorithm, standard line
bch
- 用C语言实现BCH码的编码和译码，译码是用BM迭代算法。-BCH codes in C language coding and decoding, iterative decoding algorithm with BM.
Analog-Circuits--4Ed(Tongshibai)
- 模拟电子技术基础第四版，带课件和习题答案，童诗白著，带书签-Analog Circuits 4th Edition
PCIE_V5
- PCIE_V5是一个完整的VC工程，用于xilinx Virtex5 FPGA的PCIe板卡下DMA数据读取，只能在Win xp下运行，板卡的驱动程序需要安装WinDriver-PCIE_V5 is a VC++ project, which is used to ingress massive data from PCIe board based on Virtex5 FPGA through DMA interface. Install Windriver to offer the boar
bch_verilog
- bch(255,239)编码算法的verilog实现，综合仿真通过，与matlab仿真的结果一致-bch(255,239)，using verilog
digital_tsmc018
- 180nm数字教学库，内含各种标准数字单元-180nm digital lib for education, including standard cells
AxiPC
- fpga axi测试程序,可测试符合axi协议的ip核-fpga AXI4 TEST routine，can be used to test ip which is in amba.
FaceDetection
- 基于adoost的fpga人脸检测程序，代码采用了verilog编写，用的是xilinx的virtex5芯片-face detection based on adboost. verilog is used，and virtex5 it isimplementated on virtex5.
Motion_control
- 用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法-Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm
Bit_synchronization
- 这是一个位同步的FPGA完整代码，是用Verilog写的，其中包括分频、时钟、时钟提取等各模块以及顶层文件，做调制解调的朋友可以-This is a synchronous FPGA complete code is written in Verilog, including frequency, clock, clock extraction module and the top-level file, do the modulation and demodulation of a frien
I2C-peizhi
- 利用i2c配置adv7180 将模拟信号转成数字信号bt656-i2c configuration adv7180
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V