资源列表
ram4
- VHDL 程序实现的 ram4 是一个四输入，四输出的 ram模块，在lmp_ram_dp 的dual ram 基础上扩展而成 完成一次操作需要5个时钟周期-VHDL ram4 the program is a four input and four output ram module, lmp_ram_dp in the dual ram from the expansion on the basis of a complete operational needs five clock
DIGITAL
- use grapcic Dos C pain digital clock
at25f4096
- AT25F4096的SPI通信，跑起来海有点问题写的没问题，读得有问题-AT25F4096 the SPI communications, running up the sea is something wrong with no problem writing, reading problems
watch_dog
- 看门狗的verilog源代码，项目的一部分，绝对正确，测试通过。-Watchdog of the Verilog source code, part of the project, is absolutely correct, the test.
wtem
- 简单的排队算法，还不是很全面 对初学者有所帮助
bei
- 应用VHDL语言写的倍频器，通过对高频信号的分频得到较低频率信号的倍频-Applications written in VHDL multiplier, high-frequency signals through low frequency signal divided by the frequency
ctrl_PWM
- 舵机控制源程序，属于单舵机控制，PCI总线实现。-Steering gear control source, belonging to a single steering control, PCI bus.
Keypad_51
- 基于8051单片机的 PS/2键盘的扫描程序，使用keil c51编译。-Based on 8051 of the PS/2 keyboard, scanner, using keil c51 compiler.
adder1
- 此源代码是基于Verilog语言的“与-或-非”门电路 、用 case语句描述的 4 选 1 数据选择器、同步置数、同步清零的计数器 、用 always 过程语句描述的简单算术逻辑单元、用 begin-end 串行块产生信号波形 ，有广泛的应用，比如编码器领域。-This source code is based on the Verilog language, " and- or- not" gate, with the case statement described in
c10_QPSKSA
- its code in matlab for qpsk modualation and demodulation
quanjiaqi-verilog
- 基于verilog语言的编写的全加器，基于verilog语言的编写的全加器-quanjiaqi
svgen
- 此代码是电机矢量控制SVPWM系统中进行扇区判断的CCS官方源码。-This file is about code for SVPWM to detect sector in which motor rotor is operating when contorlling motor.