资源列表
vhdl-devider
- 基于vhdl的分频器设计，分频器在数字系统设计中应用频繁-VHDL-based design of the divider, divider in the digital system design applications frequently
12
- 数字钟，能够显示时分秒，整点报时，差10秒整点时开始报时。-A digital clock that can display minutes and seconds, the whole point timekeeping, poor start 10 seconds the whole point timekeeping.
seg7_disp_test
- seg7 display testbench
int_div
- 基于VHDL的任意分频模块，利用Quartus II 9.0编译通过，并用示波器观察可行-VHDL-based modules of any division, the use of Quartus II 9.0 compiler, and the possible use of an oscilloscope
STM32reset
- STM32 关于复位类型的判断及软件复位的代码编写-STM32 on reset and software reset to determine the type of coding
tongbu_jian
- ＦＰＧＡ在通信上的运用：基于VHDL的同步头“0101010”检测指示模块-Application of FPGA in communication: VHDL based synchronous head "0101010" detection indication module
2407sciJIANYITONGXUN
- 关于DSP2407的SCI简易通讯，RS232通讯，基本通讯，内容自己修改-Easy on the DSP2407 SCI communication, RS232 communications, basic communication, content, modify their own
chap9_3
- 基于RBF神经网络整定的PID控制 大家互相学习，交流-RBF AND PID CONTROL
Ch8
- 《Verilog HDL数字系统设计及仿真》第八章有限状态机的设计源代码-" Verilog HDL design and simulation of digital systems." Chapter VIII of the finite state machine design source code
FIFO
- First Input First Output的缩写，先入先出队列，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。-The abbreviation of the first input first output, the first in first out queue, which is a traditional sequential execution method, first enter the command to finish and retire
yejing1602xiaanshixiaochengxu
- 51单片机开发板液晶1602的显示小程序。能让液晶屏1602显示一些字符。-51 1602 microcontroller development board LCD display applet. 1602 LCD display allows some characters.
vending-machine
- to increase the speed/Performance of the system the UT (Urdhva Triyambhayam) multiplier is used. UT Multiplier [10] is an cient methodology of Indian mathematics as it contains 16 SUTRAS (formulae). A high speed multiplier design by using Urd