资源列表
CPLD读取ADS7886
- CPLD读取Ti串行ADC芯片ADSL7886的Verilog代码
processor simulation
- amu part
uart
- st8s 串口程序,提供开发ST单片机参考!-st8s serial program, providing ST MCU development reference!
control
- vxworks下对串口的一些底层操作,可以-under vxworks serial number of the underlying operating
reveal
- 自动检测 示波器 的 输入频率 信号 的 VHDL 的 源代码-Automatically detect the input frequency signal oscilloscope VHDL source code
dual_port_rom
- dual port ram, it is having two data lines and two address lines at a time we can access two data from the two data lines
vcPP
- 目标跟踪histogram是一个24位的灰度数组,长度是2的24次方。此函数用于统计24位彩色图像的直方图(但这并不是一个能够独立使用的函数,有全局变量), 方法是定义了一个移动的跟踪窗口(trackwinwidth x trackwinheight). -Target tracking 自动检测中英文中译英英译中百度翻译 翻译结果(中 > 英)复制结果 Histogram is a 24 bit gray array, length is 2 to the powe
PWM
- 用于红外脉冲调制发射的程序,可将信号调制为38khz-hongwai fashe
dualram
- 本文件给出了一种双口RAM的代码,开发语言为verilog。测试可用,欢迎下载-This document gives a dual-port RAM code verilog development language. Test is available, welcome to download
load--clr-register
- 带load、clr等功能的寄存器 VHDL语言编写,亲自运行,成功-Register VHDL language, with features such as load, clr personally run
ADtest
- FPGA与ADS822通信,控制ADS822采集波形,并通过DA输出显示-FPGA communicates with ADS822, control ADS822 waveform acquisition and output display by DA
test.asm
- Generic ASM code taken Lexotan-Generic ASM code taken Lexotan