资源列表
DE2_PWM
- RC servo controller system using DE2
SFIFO
- 可以实现任意位的同步FIFO的verilog实现-the verilog code of a common SFIFO
rom16_1_16
- A basic 16 by 16 ROM memory
test5
- 利用单片机矩阵键盘扫描在数码管上显示1，4，9，16，25-利用单片机矩阵键盘扫描在数码管上显示1，4，9，16，25...
counter_net
- counter verilog code
display
- 八段数码管显示驱动程序，可用于多位显示的扩展-Eight out digital display driver can be used for the expansion of a number of display
Code
- Water level Controller using PIC
PWM_Generator
- PWM generation from PIC 16F877 using mikroPascal
FPGA_multiplier
- 本源码是用verilog语言编写的FPGA乘法器，可以输入两个8位数据，出输16位结果。-The source code is written in verilog FPGA multiplier, you can enter two 8-bit data, the output 16 results.
ADS1271
- VHDL的接口程序 24-bit 105ksps ADC 型号是：ADS1271 绝对稳定-VHDL interface program 24-bit 105ksps ADC models are: ADS1271 absolutely stable
aaa
- 24位加法计数器，每一个信号的上升沿将使得计数器加1，实现从0 -1 -2 -3…… -22 - 23的循环计数器。-24 States adding type counter， every rising-edge signal increases the counter, and making sequence 0-1-2-...-22-23 cycled.
flowprogram.h
- flow meter 0-10l with 8051