资源列表
adder
- vhdl adder with two input 4-bit and output of 4 bits and carry
m_vhdl
- 设计一个伪随机序列发生器,采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值(程序中设定好四种非零初值可选)。-Design a pseudo-random sequence generator, using the generating polynomial 1+ X ^ 3+ X ^ 7. Requires a RESET terminal end and two control registers to adjust the initial valu
yiweishumaguan
- 自己做的用指针做的移位数码管显示,完全原创-Do their own make shift with a pointer to digital control, completely original
FIFO
- FIFO,双端口数据存储器,实现数据先入先出的存储器件-FIFO, dual port data memory, data FIFO memory device
juntos
- serparser vhdl file download gggggggggdstrhjtdsjtdc
4X4
- ANOTHER 4X4 EXAMPALE
ALU
- ALU 与ALU控制器 实验 VHDL Verilog 语言设计-ALU VHDL Verilog
sell
- 自动售饮料机代码,信号定义: clk: 时钟输入; reset: 为系统复位信号; half_dollar: 代表投入5角硬币; one_dollar: 代表投入1元硬币; half_out: 表示找零信号; dispense: 表示机器售出一瓶饮料; collect: 该信号用于提示投币者取走饮料。 -Automatic beverage code
queue
- Queue program in C using Arrays
fet140_1
- MSP430F Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK= n/a, MCLK= SMCLK= default DCO ~800k-MSP430F Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK= n/a, MCLK= SMCLK= default DCO ~800k
dtc
- 可以根据不同的传输要求,实现命令字和数据字的精确同步控制,编码中包含了时钟和数据信息,在传输代码信息的同时,实现了时钟信号的同步传输-According to different transmission requirements, the command and data words to achieve precise synchronization control, the encoding of the clock and data information contained in th
addsub
- This code implement add or sub between 2 number