资源列表
second&clk
- 开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路
Music_altera
- 采用Verilog HDL设计，在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率，演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
SPI串口的内核实现spicore
- SPI串口的内核实现spicore SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore
cpld_bus
- CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
Convolutional encoding and Viterbi decoding with k
- 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
4x4的数据选择器
- 用vhdl的4x4的数据选择器，在maxplusII下编译、仿真通过。是构成大型数字电路的重要部件。适合vhdl初学者分析学习。-4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to lear
pci 的vhdl 源代码
- pci 的vhdl 源代码-The source code of PCI VHDL.
SECLOCK
- 我从一本书上抄来的 但用MAX+PLUSII编译有些问题 初学者 见谅-from a book copied but with the MAX PLUSII compile some of the problems beginners forgiven
STUDY_CPLD.RAR
- 这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.
t80
- Configurable cpu core that supports Z80, 8080 and gameboy instruction sets
ELEC_LOCK
- 4位电子密码锁，带键盘扫描、按键防抖动、LCD驱动编译码-four electronic password lock with a keyboard scan button shake, LCD driver encryption
USB枚举
- ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface