资源列表
pipelined_fft_64-master
- Pipelined FFT/IFFT 64 points (Fast Fourier Transform) IP Core User Manual
SDRAM
- 基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
PMD
- 跑马灯和状态机的结合，利用状态机控制灯的各种状态的切换与闪烁(Switching and scintillation of various states using a state machine to control the light)
28_adda_test
- 在Quartus平台上，完成了AD、DA的Verilog实现，测试结果准确。(Use Verilog to realize the function of AD and DA)
03my_mux
- 器件EP4CE6F22C8N2选一数据选择器(Choose device EP4CE6F22C8N2 data selector)
04my_decode
- 器件EP4CE6F22C8N 2-4译码器译码器(Device EP4CE6F22C8N 2-4 decoder decoder)
PAL25fps
- 标准pal制式显示 768*576，25hz(PAL code Standard pal mode displays 768*576, 25Hz)
module demultiplexer1
- Verilog code for demultiplexer
Module fulladder1
- Module full adder behavioral modelling
Program of 4 to 2 Encoder
- Verilog code for encoder
Program of 2 to 4 Decoder
- Verilog code for decoder
DDS
- DDS直接数字合成器，里面包含相关的顶层文件，加法器，D触发器，mif文件(DDS direct digital synthesizer, which contains related top layer files, adder, D trigger, MIF file)