资源列表
dianzheng6.2banben
- 8*8点阵的实现，循环显示vhdl四个字母-8 * 8 lattice the realization cycle shows vhdl four letters
qiangdaqi4ren7.1
- 四人抢答器的实现，主持人按键清除按键，按开始键，100秒倒计时答题时间-four Responder the realization host keys to remove the keys, according to begin key 100 seconds to answer in the countdown time
pingche
- 简易数字频率计，数码管显示，VHDL语言-simple digital frequency meter, digital control, VHDL
mimasuo2S50
- 8位密码锁的实现，初始状态默认为密码正确，密码输入正确方可设密码，以后必须按对密码才可重设-8 password lock the realization of initial state defaults to the correct password, the password can input the correct password. After the password must be re-established before
Bintograyconverter
- 二进制到格雷码转换ASD ASD ASD-binary Gray code conversion to ASD ASD ASD ASD ASD
crc_32_16
- crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
vhdlduogelizi
- 多个VHDL程序,跟大家参考,交流,谢谢,了,大家 -many VHDL procedures, with reference exchange, thank you, and we
vhdlfinishcpu
- 用vhdl实现简单cpu的功能,能够很好的帮助特别是初学者学习vhdl的功能!-with vhdl cpu to achieve simple function can be very helpful, especially beginners learning vhdl function!
mipsinverilogandvhdl
- mips prcessor in Verilog and vhdl-mips prcessor in vhdl and Verilog
ddschengxu
- dds程序 有原理图 代码 哈哈 dds程序 有原理图 代码 -dds procedures diagram code says dds procedures diagram code
DJDPLJ_T
- 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成，能精确检测从1--100M频率，误差极小且恒定。-the VHDL source code from the top module, measuring frequency module, driver modules, modules, LCD display module, reduction modules, can be used to accurately detect from 1 -- 100M
verilog111
- verilog 的东西好好用的呢，那是verilog 学习者的必备东西哦-verilog things properly used it, it is an essential learners verilog things oh