资源列表
vhdl-2
- UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
gold
- SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。用来生成gold码。-SRL16 Virtex devices is a shift register lookup table. It has four input used to select the output sequence length. Use XCV50-6 device, occupying a total of five Slice.
VHDL-Clock
- 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
clock_CPLD
- 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note / / / moderator, development environment there's no MaxPlusII.
dfgg
- 请先删除编译后的debug/release目录以减少压缩包大小-compiled the debug / release directory to reduce the size of compressed
RS232-for-vdhl
- RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
generic_fifo
- 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
100vhdlexample
- vhdl的一些简单例子,适合初学者学习使用,大家互相指正-instantiate some simple examples, suitable for beginners to learn how to use so that we can correct
BBSdfbdgdr
- 如果遇到MD5加密文件，而又不知道密码的， 请在数据库中换上这组加密的数据吧 16位：7a57a5a743894a0e 32位：21232f297a57a5a743894a0e4a801fc3 那么密码就是admin-if they MD5 encryption, and do not know the password. please database with a group of encrypted data it 16 : 7a57a5a743894a0e 32
yyue
- 音乐小程序，初学者使用参考-small procedures, the use of reference beginners
async--RS232
- async--RS232VERILOG HDL原代码-async -- RS232VERILOG HDL source
Quaalu
- ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲-ALU arithmetic logic unit to achieve a simple, using VHDL language, can be additive, subtractive, and the place and move around only one clock pulse