资源列表
equlizer
- 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integra
TRAFFICCONTROL
- 该程序是用一片HDPLD和若干外围电路实现的十字路口交通控制器,其中包含顶层图形文件和源文件以及仿真波形-the program is a HDPLD and a number of external circuits to achieve a crossroads traffic controller, these include top graphics files and source documentation and simulation waveforms
plus_lib
- 这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形-This is a level VHDL design of a Jiujiuchengfabiao source, also includes simulation waveforms
ISE_uart
- 自己在ISE下用VHDL写的UART，简单，易懂-in ISE using VHDL was the UART, simple, understandable
ddr_verilog_xilinx
- 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
VHDL_
- vhdl一些重要的例子 内容很丰富 无解压密码-instantiate some important examples of very rich content without extracting passwords
zldjkzjq
- max+plusII下编成的直流电机控制器vhd-under monument of the DC motor controller vhd
ongame
- 一个游戏 the hardware for the game includes a number of displays, each with a button and -- a light, that each represent a bin that can store marbles (beans). -- -- The display indicates the number of marbles in each bin at any given time. --
csxl
- 相应加法器的测试向量（test bench)-corresponding Adder test vector (test bench )
jfq1
- vhdl和verling hdl 的加法器-VHDL and the Adder.
ztj
- max+plusII下的使用列举类型的状态机-max plusII use of the listed types of state machine.
jcq
- max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd