资源列表
hdl_coding_style
- HDL编程风格，很有用,希望对大家有所帮助。-HDL programming style, very useful, we want to help.
wavefetch
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the waveform window or window List
fpgavhdldaima
- 用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
tbxsp010
- 用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
yyin
- 这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down
beipin
- 用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
source_files
- FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
digitalsystemDesign
- 第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-f
statemachine
- 自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone's attention.
u-uart
- 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
CORDIC01
- CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
ethernet[1].tar
- 一个以太网卡的硬件描述，可以参考进行设计网卡芯片。-an Ethernet card hardware descr iption, reference card chip design.