资源列表
shukongfenpinqi
- 数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the
ADCINT
- 此程序基于ADC0809,它是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中。-Connection between ADC 0809, it was the eight CMOS A / D converters. Tablets containing eight analog switches, control eight of analog converters enter a Chinese.
baijinzhi
- 利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.
FPGApro
- VERILOG HDL 实际工控项目源码 开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2
pwmled
- 一个霹雳灯的Verilog源程序，用PWM原理实现，产生了LED灯的渐弱效果-a thunderbolt lights Verilog source files, using PWM principle realized, LED lights have a gradual effect of the weak
cordic_vhdl1
- 利用cordic实现直角坐标与极坐标的转换，用vhdl实现-use cordic achieve very Cartesian coordinates with the conversion, with vhdl achieve
cordic_vhdl2
- 利用cordic实现三角函数的计算，用vhdl实现-use cordic achieve trigonometry calculations, using achieve vhdl
my_ramlib_06
- 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL descr iption, such as FIFO, Dual Port RAM, etc.
count60_dec_bcd_led
- 是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.
ata_6_DMAIPCORE.tar
- 最新的ATA-六总线协议源代码参考，实现DMA,PIO模式，可挂CDROM,IDE硬盘，CF卡．-the latest ATA-6 bus protocol source code reference, achieving DMA, PIO Mode, can be linked to CDROM, IDE hard drive, CF card.
SDmmcfpgaconfig.tar
- MMC卡的VHDL源代码实现，经过大批量生产验证-MMC card VHDL source code to achieve, through large-scale production test
ps2_soc2
- PS2的源代码VHDL语言实现，可以和计算机直接连接．做鼠标键盘接口．-PS2 source VHDL, and can be connected directly to the computer. So the mouse, keyboard interface.