资源列表
firISPdesign
- fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware descr iption of the filter language , including the VHDL language and verilog
IP_SPI
- spi总线的vhdl代码，试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers.
Verilog_FPGA_fp
- 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
verilog_latch
- verilog实现锁存器，共有四个文件，包含测试文件-verilog achieve latches, a total of four documents, including test paper
verilogfifo
- verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
verilog_multiplier
- verilog实现16*16位乘法器，带测试文件-verilog achieve 16 * 16 multiplier, with test documents
VHDLDPLL
- 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
HXRJTD
- 这是本人在Max plus2环境下用VHDL语言编的交通灯控制程序。做EDA课程设计的朋友可以下来参考参考。-This is my Max plus2 environment with VHDL addendum to the traffic lights control procedures. EDA design courses so friends from the reference reference.
DDS_SINWAVE
- matlab下，用dspbuilder实现dds模块产生正弦波的源码，-Matlab and used to achieve dds dspbuilder produce sine module source code,
PSKmoudel
- matlab下，使用dspbuilder实现的psk调制模块的源码-Matlab, the use of dspbuilder realized psk modulation source module
ASKmoudel
- matlab下，使用dspbuilder实现的ask调制模块的源码-Matlab, the use of dspbuilder realized ask modulation source module
comple_mult
- matlab下，使用dspbuilder实现的复数乘法器模块的源码-Matlab, the use of the plural dspbuilder achieve multiplier module FOSS