资源列表
DIGITALCLOCK
- 多功能数字种 可实现校时 闹钟 整点报时等功能(Multi-function digital species can realize the function of time alarm clock and other functions)
fifo_test
- fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
OSVersion
- os version Descr iption
file2
- factorial file for the fortran pascal
xi
- xilinx screenshot vhdl verilog
8
- filter fir tap implementation
3M
- 在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal
Writing Testbenches using System Verilog
- Material to learn how to use system verilog and how to write testbenches for verification.
Serial to parallel vhdl
- SERIAL TO PARALLEL VHDL CODE
clock_test
- 采用verilog语言，运行在FPGA上的时钟程序，包括小时、分钟、秒，进行计时(Clock programs, including hours, minutes, seconds)
XC6SLX9 Mini Board Documents
- spartan 6 fpga custom board schematic and component list
v3
- mojo v3 complete eagle schematic