资源列表
crc_16
- 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
veriloghdl快速入门
- verilog hdl 快速入门,里面包含很多有用的硬件描述语言的程序-Verilog HDL Quick Start, which contains many useful hardware descr iption language procedures
FPGA_Design_Guide_Chapter1_Westor
- 可编程器件，如果有问题的可以和我直接联系-programmable devices, if a problem can be directly linked to and I
红绿灯控制
- 红绿灯的控制，关于红绿灯的变化顺序，计算变化时间等-traffic light control, the changes on the order of traffic lights, changes of time
加法
- 测试向量波形产生：VHDL实例---加法器源程序 -test vector Waveform Generator : VHDL example -- Adder source
blaster-wh
- 自己做的Altera下载线，老早了，protel98制板。-wh-own download Altera's line, long ago, protel98 Cricket. - Wh
Evita_Verilog
- Verilog 的非常好用易懂的教学软件。-Verilog very handy and easy to teaching software.
Evita_VHDL
- VHDL 的非常好用易懂的教学软件。大家试试看。-VHDL very handy and easy to teaching software. We try.
CPLD_DMA
- 这是一款USB接口ISP1582器件实现DMA传输的辅助电路的硬件设计源代码-This is a ISP1582 USB device DMA transmission of the auxiliary circuit hardware design source code
RAMINCREASE
- 这是利用ＣＰＬＤ做ＤＳＰ的存储器扩展的源文件。-CPLD This is done using the DSP memory expansion of the source document.
primetime
- 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
mt48lc2m32b2
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified