资源列表
WERDTEST
- CCD DRIVER 本软件用于线性CCD 传感器时序控制 -CCD DRIVER software for the linear CCD sensor timing control
Sparc_leon_VHDL
- 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
8051inVHDL
- 一个8051的VHDL代码，可完整编译， 但不保证版图映射成功，可作为设计微处理器的参考-a 8051 VHDL code can be compiled integrity, but it does not guarantee success territory mapping, the microprocessor can be used as a reference design
VHDL_freerisc8
- 一个8位RiSC单片机的VHDL代码， 具有很好的参考价值。-an eight RiSC SCM VHDL code, is a good reference value.
VHDL_100Examples
- 北京里工大学ASIC设计研究所的100个 VHDL程序设计例子-Beijing University Institute of ASIC design hundred examples of VHDL Design
tbcpu8bit2
- 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
uart2
- uart 通用异步接受机 编译环境为quartus-UART Universal Asynchronous Receiver and build environment for Quartus
Traffic_Light_Final
- Traffic light written with Verilog-written with Verilog
final_code
- mining source code written in Verilog
Butterworth_IIR_Filter
- DSP中巴特沃思滤波器的设计使用Verilog编写.
Altera-AHDL语言设计的PCI总线Core
- Altera AHDL语言设计的PCI总线Core,很难得的PCI设计资料-Altera AHDL design Core PCI, the PCI is difficult to design information
crc_16
- 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.