资源列表
clk_divide_3
- VHDL语言编写三分频，可以扩展实现任意奇数-VHDL prepared three frequency can be extended to achieve arbitrary odd
quartusii
- 推荐!!!!!学ASIC相当不错的教程!!!!还是可以看看的-recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!
calendar_clock
- 用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能-using HDL to write electronic calendar, it shows the year, month, day and time, with alarm function
88_arms_counter
- vhdl源程序,可在quartus中编辑测试，仿真。-VHDL source code can be edited in Quartus test, simulation.
68_alarm_controller
- vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
78_alu_input
- vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
key_scan1
- 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
ProgramText
- we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.-we will use the cables Spartan3 FPGA design to a specified counter using the VHDL language.
hdb3_VHDL
- hdb3 using language VHDL-Indoor using VHDL language
signalgenerater
- 一个简单的多种信号的发生器 包括正玄，锯齿，阶梯等，使用时用quartus 4.0以上版本打开-a simple multiple signal generator including Shogen, sawtooth, the ladder, when used with the above version 4.0 Quartus open
2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
ceshixiangliang
- vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples --- corresponding Adder test vector (test bench). Txt