资源列表
vhdlprogram
- 用复杂可编程逻辑器件(CPLD)实现的数字钟控系统-with complex programmable logic devices (CPLD) with a digital clock control system
TI6713DSKVHDL
- TI6713浮点DSP的DSK的VHDL。比较全面。可以编译运行。-TI6713 floating-point DSP DSK VHDL. More comprehensive. Compiler can run.
n_dc_motor
- vhdl实现的直流电机控制器 通用程序 对不同fpga/cpld，可能需要修改部分源代码。-VHDL achieved DC Motor Controller General of different procedures they simply / cpld. may need to amend some source code.
source_verilog
- verilog shi 实现的加法器（8位）适用于初学asic -Verilog realized Adder (8) applies to beginners blends
sdramcore
- sdram控制的内核，高手编的，已经调试过了，没有错误-SDRAM control of the kernel, the top series, has been tuned, no errors
air_controller
- 此为一个空调控制器，是利用FPGA来实现的，他能够完成对室内温度的调节。-this as an air-conditioning controller, is to use the FPGA to realize that he can complete the indoor temperature adjustment.
MAX_II_board_schematics
- Altera MAX II 开发板原理图-Altera's MAX II development board schematics
CPLD_CCD
- 实现基于CPLD的CCD采集系统设计源码-based CPLD CCD Acquisition System Design FOSS
vhdl_examples
- vhdl语言例程集锦，大量丰富的程序代码，对于VHDL学习很有帮助-VHDL language routines magazines, large variety of code for VHDL helpful learning
veriloghdl135
- vhdl的学习资料，教程，一起进步，共勉-VHDL learning materials, curricula, progress together, share!
color_space_converter
- verlog 编程 色彩空间转换 有测试文档-verlog programming color space conversion is testing documents
ad_DCT
- verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores