资源列表
xiaolizi1588
- ic读卡器 能读ic电话卡并按时记费-ic reader can read ic phone cards and charged fees on time. .
8051IPCORE
- VHDL写成的8051IP核，仔细看能有不少收货-written in VHDL 8051IP nuclear, look very carefully to have a receipt
bicount
- 完整的双向计数器VHDL 程序 大家参考-integrity of the two-way counter VHDL reference procedures
qep_data_bus
- 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的-address bus interface based on the four frequency signal encoder interface FPGA Verilog HDL
eclock
- MAXPULS II 下VHDL实现多功能电子钟的源代码，包括时钟，秒表，日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar
VHDL_processor
- 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL descr iption of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
VHDL_Examples_for_education
- VHDL代码编程,集合了众多优秀的实例,胜过任何一本书的例子,作为教学或程序开发中调用非常合适!-VHDL code programming, a combination of a large number of outstanding examples are better than any one book's examples, as a teaching program or call very appropriate!
quanjiaqi
- 全加器的详细设计思路和用VHDL语言编写的详细源代码-increase for the whole of the detailed design ideas and the use of VHDL for preparing a detailed source code
mcode
- 一个典型的m序列发生器，生成m序列:1110010-a typical sequence generator m, m Sequence Generation : 1110010
mux2
- 二进制数据或者频率信号选择器，判决时钟满足低频条件-binary data or frequency signal selectors that the judgment low-frequency clock to meet conditions
fifo88
- 8*8位的先入先出（fifo）数据缓冲器的vhdl源程序-8 * 8 of the first-in-first out (FIFO) buffers the data source VHDL
sspp
- 串行输入信号经内部处理后，实现并行信号输出的功能-serial input signal by the internal processing, parallel signal output function