资源列表
s25fl040a
- ST S25FL040 Sefial Flash Verilog Model
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
JPEG
- JPEG解码(Verilog)源码，详细，高效。-JPEG decoding (Verilog)
AMI
- 在ISE软件环境下，用Verilog HDL语言实现通信中的AMI码的编码和译码，并有仿真波形。-In the ISE software environment, using Verilog HDL language for communication in the AMI code encoding and decoding, and a simulation waveform.
cdma
- 使用verilog在QII系统中开发的一个简单的4用户CDMA系统。-In QII system using verilog developed a simple four-user CDMA system.
4bit-adder_verilog
- 4位全加法器的modelsim工程带testbench-Four full-adder modelsim project with testbench
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
dianziqin
- 多功能电子琴 PS2键盘作为琴键 VGA同步显示播放的琴键-Multi-function keyboard PS2 keyboard keys as keys to play VGA synchronous display
NIOS_VGA
- 某高人自己写的VGA程序，VERILOG格式，经测试，修改后可用。-An expert to write the VGA program, VERILOG format, tested, modified available.
system_verilog-manual
- systemverilog教程，很精简，但很准确-systemverilog tutorial, very lean, but very accurate
AD9850
- DDS直接数字频率合成AD9850源代码，能输出0到40M分辨率为1K的正弦波形。-DDS Direct Digital Synthesizer AD9850 source code, can output a resolution of 0 to 40M 1K sine wave.
led
- 基于quartus II 软件用vhdl语言写的交通灯实验 源代码、最终生成文件全程奉献-Quartus II software-based language used to write vhdl traffic light test source code, the resulting file full dedication