资源列表
chip-SRAM-communication
- Verilog编写FPGA与片外SRAM通信模块，内含源代码，希望对大家有所帮助。-FPGA in Verilog-chip SRAM with communication modules, including source code, we want to help.
VHDL-digital-clock-
- VHDL编写的数字钟，采用元件例化的方法，可实现调秒 调分 调时 报时 闹铃的功能 开发板使用的是EP3C16Q240C8-Digital clock written in VHDL, using the example of the way components can be adjusted to achieve sub-second tone when the alarm tone Times feature development board using EP3C16Q240C8
RC6-block-cipher-using-VHDL
- VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped
Verilog
- 针对Verilog语言，提供了135个经典的示例程序代码，从简单到复杂，一步步的深入。-For the Verilog language, providing 135 classic example code, from simple to complex, step by step in depth.
sim_nandflash
- 完成FPGA对NAND FLASH的读写操作，整个控制构架搭设完毕，可以添加新的功能。板级验证正确，有仿真波形和三星NAND FLASH 手册。-FLASH read and write operation to complete, board-level verification is correct for the new to FLASH friend, a simulation waveform and Samsung FLASH Manual
PWM
- pic单片机的脉冲宽度设置程序，虽然程序非常的简单，但是能够自由的调整脉冲宽度-pic microcontroller pulse width of the setup program, although the program is extremely simple, but the freedom to adjust the pulse width
FPGA--VerilogFIFO
- FPGA串口通信程序 基于fifo读写的串口通信程序-FPGA serial communication program is based on the serial communication program to read and write fifo
cd_player_vhdl
- 全套日本CD Player的FPGA设计制作源码(用VHDL编写)。在ise上运行。-Japanese CD Player complete set of FPGA design source (using VHDL). Ise on the run.
my
- 64位数据的CRC-32校验的，Verilog实现，算法并行优化-64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm
xc2v_verilog
- MIMO Simulation VHDL code
xc2v_vhdl
- Verilog Code for MIMO system
Xilinx_PCI_Express_IP_project
- Xilinx公司PCI Express IP核应用参考设计