资源列表
SPtransform
- Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
FFT_CORE
- FFT算法的VHDL语言实现 可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
cpuTerminate
- 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
I2C0001
- 基于FPGA的I2C程序0001,很不错的论文及程序，，大家快下啊-FPGA-based procedures I2C 0001, a very good paper and procedures, we quickly under ah
i2c_master_bit_ctrl0002
- 基于VHDL的I2C程序0002,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0002, a very good paper and procedures, we quickly under ah
i2c_master_byte_ctrl0003
- 基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0003, a very good paper and procedures, we quickly under ah
i2c_master_top0004
- 基于VHDL的I2C程序0004,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0004, a very good paper and procedures, we quickly under ah
tst_ds162100005
- 基于VHDL的I2C程序0005,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0005, a very good paper and procedures, we quickly under ah
pingpangqiu
- 用max+plusII编写的vhdl程序 乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game
DataConverter
- 利用VHDL语言实现8位到32位的双向数据转换-use VHDL 8-32 two-way data conversion
vhdl_8cpu
- VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code
altera_lcd_controller
- quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE