资源列表
shuzhizhong (1)
- 数字时钟的FPGA设计,对学习FPGA有很大的帮助,希望大家能采纳(FPGA design of digital clock has great help for learning FPGA. I hope everyone can adopt it.)
循环码
- 这是对于循环码编码器的语言,希望对大家有帮助(This is the source code for cyclic code coding, I hope to help everyone)
RGMII_RECEIVER
- This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.
Up_Down_Counter v1.0
- FPGA Up/Down couner Module
Multi_cpu
- 多周期CPU自己课程大作业做的,亲测好用,verilog语言,适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
Single_cpu
- 单周期CPU自己课程大作业做的,亲测好用,verilog语言,适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
spi_8r8w
- 同时实现多个SPI从设备的连续读写,读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
and_gate
- ALU设计与开发,四位的,简单可仿真,内部里面有text班车(ALU design and development, four bit, simple and emulation)
mj10
- 实现门禁系统,可以做网店实战的项目,对接数据库,不过里面没有数据库想对应的测试数据(The implementation of the entrance guard system, can do online shop actual projects, docking database, but there is no database to corresponding test data in it.)
《Verilog HDL设计与实战》配套代码(1)
- 《Verilog HDL设计与实战》配套代码 verilog源程序(Verilog HDL design and actual combat code Verilog source program)
DVCon_Europe_2015_T01_Presentation
- Advanced UVM Tutorial by Verilab
PPM
- 对4比特二进制数据进行PPM调制,位宽可修改(PPM modulation for 4 bit binary data)