资源列表
veriexamples
- 非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful
CALCULAT.ZIP
- verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
xcv
- verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... a
S3Demo
- 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS / 2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
SystemVerilog_FIFO_Channel
- 2004 SNUG of systemverilog
produce
- vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation
LDOTESTSYSTEM
- 这是一个GPIB源程序代码,里面有硬件相对应的代码-This is a GPIB source code, which corresponds to a hardware code
200691151948398
- 这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范-This is a GPIB programming also introduced the article and introduce GPIB norm
n2cpu_nii5v3_01
- 这是介绍嵌入式开发相关的资料。有总线与内存的操作-introduced Embedded Development relevant information. Bus and a memory operation
Div20PLL
- 使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
dds_fpga
- DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-re
serial_ppga
- 异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control