资源列表
ADC_handle
- 针对ADC器件AD9226的数据采集处理流程，针对手册时序做的有效数据输出控制。Verilog HDL- ADC AD9226 data acquisition device for processing flow for the manual timing do valid data output control.Verilog HDL
32-bit-division-design-In-Verilog
- 32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
ahb_master
- AHB master system generator in verilog
RAM
- Nios ii双口ram,用于MCU通过nios ii进行双口ram通信,verilog格式.-Nios II dual port RAM, for MCU dual port RAM communication, through the Nios II Verilog format.
PISO-NEW
- THIS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.-THIS IS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.
CAN
- 包含CAN协议讲解与CAN协议控制器的verilog实现(含有testbench），该实现模仿SJA1000架构，接口完全一致。压缩包中还包含SJA1000的手册与应用指南，非常好的CAN学习资料。-CAN protocol controller implemented in Verilog（contain testbench） & instruction of CAN protocol & datasheet and user manual of SJA1000
Sim_model
- this the simulation model for nand flash-this is the simulation model for nand flash
ug898-vivado-embedded-design
- Vivado Design Suite User Guide 是学习Vivado 入门文档，源自xilinx，权威易懂-Vivado Design Suite User Guide 是学习Vivado 入门文档，源自xilinx，权威易懂，
mt48lc32m16a2
- SDRAM的仿真模型Verilog。用于美光mt48lc32m16a2，可在ModelSim下用。-Simulation Model of SDRAM
FPGA_CODE-AD7765
- 该资料基于FPGA，采用verilog语言，完成AD7765芯片的模数转换，AD7765可实现24位精度的高速采集，在出自信号处理中占有重要的地位-The information on FPGA, using verilog language, complete chip AD7765 analog-to-digital conversion, AD7765 can achieve 24-bit precision high-speed acquisition, plays an importa
CY7C68013A_board_test
- 该资料基于FPGA实现USB2.0的高速传输，即CY7C68013A芯片的数据传输，包括FPGA与上位机之间数据的相互传输，CY7C68013A的传输速率最高可达480M/S。-The FPGA-based high-speed data transmission USB2.0, that CY7C68013A chip data transmission, including the mutual transmission of data between the FPGA and the ho