资源列表
猜數字，終極密碼
- verilog code 可以控制玩家數目，及遊戲模式(有兩種:猜數字 + 終極密碼) 最後結果會顯示出排名及分數
RR_SCH(Executable)
- FPGA VERILOG调度器一般包括SP、RR、WRR、WFQ等，RR调度指的是轮询调度，此种调度不带权重概念，均匀轮询进行调度。-FPGA VERILOG The scheduler typically include SP, RR, WRR, WFQ, etc., RR refers to the round robin scheduling, dispatching without the weight of such concepts, even polling scheduling.
TCAM
- FPGA VERILOG TCAM (ternary content addressable memory)是一种三态内容寻址存储器，主要用于快速查找ACL、路由等表项。-FPGA VERILOG TCAM (ternary content addressable memory) is a ternary content addressable memory, mainly used to quickly find ACL, routing entries.
mvb_altera_may-02
- altera mvb fpga sopc 设计参考文档，有一定价值-mvb fpga sopc Design scheme
1553-EncoderDecoder---Documentation
- 1553b编解码参考设计 verilog 收发-1553b encoder decoder
Verilog_add_div_multi_exp
- 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
FPGA 正交编码 verilog
- 用Verilog写的2倍频率正交编码的仿真测试程序，仿真波形已经调出
4077mt48lc32m16a2
- 美光公司提供的DDR2的verilog仿真模型和do文件-Micron DDR2 provides the verilog simulation model and do file
Svpwmm
- Verilog HDL 写的SVPWM 算法的实现，使用的是altera 风暴系列的FPGA，占用资源1w+逻辑宏单元-Verilog HDL ，SVPWM
microzed-axi-dma
- microzed (zynq) axi dma source vhdl
plus1
- 3位二进制运算器及其数码管扫描显示电路3 binary arithmetic and digital scanning display circuit-3 binary arithmetic and digital scanning display circuit
SMBus
- SMbus通讯协议的Verilog程序段，已通过Moldesim的仿真，可用-Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available