资源列表
COSTAS_LOOP
- 使用ISE12.1编写的Costas环，用于载波恢复，直接使用了IP核中的FIR和DDS模块-Use ISE12.1 written Costas loop for carrier recovery, the direct use of the IP core of FIR and DDS module
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
EEPROM2
- I2C协议的EEPROM的verilog程序，调试成功，可以根据系统的需求更改参数，程序中实现了连续读-I2C EEPROM protocol verilog program, successful commissioning, the parameters can be changed according to the needs of the system, to achieve a continuous reading program
windows-script
- 在window平台，采用脚本TCL来编译fpga的经典例子。具体的写法，见工程中的ise_flow.bat文件。如果在工作站来处理更块-In the window platform, using classic example TCL scr ipt to compile the fpga. Specific wording, see the project ise_flow.bat file. If the workstation to handle more blocks
Example2
- 一个基于FPGA的格雷码转换器的小程序，输入8位格雷码并转换结果。-A gray code converter FPGA-based small program, input 8-bit Gray code and conversion results.
component_timer_counter
- Quartus环境下基于VHDL元件例化的数字钟程序-Zhong Chengxu digital VHDL component instantiation based on Quartus environment
verilog
- 把32位的数据转换成8位数据输出，用做fpga把数据传给dsp处理-The 32-bit data into 8 bits of data output
ethernet_test
- FPGA 100M以太网UDP/IP收发-FPGA 100M Ethernet UDP/IP to send and receive
Micrium_Microblaze_uCOS-II-AXI
- 支持xilinx ise designer 14.x的microblaze AXI总线 ucosii操作系统。-Support xilinx ise designer 14.x for microblaze AXI bus ucosii operating system
7_ImageEnhance
- 基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波-System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering
13.3_Tracing
- 基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪-System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking
ACO-OFDM
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