资源列表
e011_timingdesigner
- FPGA时序设计时必备的软件。可以有效的提高逻辑设计的速度，调整设计时的时序。-FPGA design timing necessary software. Logic design can effectively improve the speed of adjustment of the design timing.
pc_cfr_test_v3_1c
- 一个关于降低现代通信系统中高峰均比信号的matlab算法，对于研究数字预失真基于FPGA实现的有一定作用！-A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!
fpga-vga
- fpga上实现vga控制不同颜色小块延45度顺时针运动-fpga vga to achieve small 45-degree movement control
11_temperature
- verilog 语言实现的温度计。 FPGA 基本教程-a temperaturer basied on verilog .
RScoder
- 基于FPGA的RS编码器设计，verilog hdl语言。-RS encoder FPGA-based design, verilog hdl language.
dso
- 用FPGA设计的数字示波器，有详细的设计过程、论文和硬件原理图-Digital oscilloscope with the FPGA design, detailed design process, paper and hardware schematics
dtmf
- dtmf 8880 tx phone ca-dtmf 8880 tx phone call
MSB_search_verilog
- 使用Verilog实现16位数据最高有效位的查找-use verilog to search msb of 16 bits data
s25fl040a
- ST S25FL040 Sefial Flash Verilog Model
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
JPEG
- JPEG解码(Verilog)源码，详细，高效。-JPEG decoding (Verilog)
AMI
- 在ISE软件环境下，用Verilog HDL语言实现通信中的AMI码的编码和译码，并有仿真波形。-In the ISE software environment, using Verilog HDL language for communication in the AMI code encoding and decoding, and a simulation waveform.