资源列表
phase_add
- 分频器，实现任意频率的分频，只需修改频率控制字,已经经过多次验证-Divider to achieve any frequency divider, simply modify the frequency control word, has been repeatedly verified
C702
- 控制HMC702的VHDL程序代码,实际使用是可以的，HMC MODE-HMC702 SPI VHDL code
Dijkstra
- 用verilog 实现求最短路的Dijkstra算法，用modelsim仿真通过，数据真确，-Dijkstra implemention with verilog base on FPGA
1-Animatie-CoCa-Cola
- Seven Segment Animation
con1
- 4 bit convoltion with vhdl.
rxmodem
- vhdl file-vhdl filebbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb
div_2
- 2分频代码，用于4路视频AD采样。原时钟为25M-2 frequency code for the 4-way video AD sample. The original clock is 25M
uart_send
- 串口发送程序，用无数设备验证过的，可靠，波特率2M，系统时钟40M-Serial transmission program, verified by numerous equipment, reliable baud 2M, the system clock 40M
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
8bit_adder_AND_4x4_Multiplier
- 位加法器的verilog程序与4×4 乘法器的verilog描述-Verilog-bit adder of the procedures and 4 × 4 multiplier verilog descr iption! ! !
ADD_SUB_32bit
- 加减法器，可实现有无符号数的加减法-Modified instruments used, can be realized whether the number of addition and subtraction symbols
ram_tb
- ram vhdl module for modelsim and vhdl design