资源列表
FPGA_SPI.ZIP
- 实现了FPGA以SPI协议传送和接受16位数据。传送过程无需Nios核干预-SPI protocol to achieve the FPGA to send and receive a 16-bit data. Nios nuclear transfer process without intervention
FPGA_design
- Altera+FPGA／CPLD设计基础篇和高级篇.pdf，详细讲解FPGA的设计过程及应用-Altera+ FPGA/CPLD Design Basics and advanced articles. Pdf, explain in detail the design process and application of FPGA
ASIC-SYNOPSYS
- 芯片设计综合经典书籍 design compiler primetime-asic synthesys
Digital_oscilloscope_VHDL
- 利用VHDL语言编写数字示波器的程序，下载入FPGA中可实现。在Quartus7.1编译环境中已经测试通过。-Digital oscilloscope using VHDL language program, download into the FPGA can be achieved. In Quartus7.1 build environment has been tested.
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或）。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se
zidongshouhuojisheji
- 本文采用Verilog HDL描述语言实现自动售货机系统的销售动作，用有限状态机进行系统状态描述，自动售货机通电复位时，自动进入系统初始状态，本文设计的自动售货机控制系统主要可以实现投币处理、计算投币总额、输出商品，输出找零、余额计算并显示等功能。-This verilog hdl describe language used for automatic machines system of action, with a limited system of state, state, the v
EPM570
- 这是ATLREA的EPM570的一个144管脚CPLD的最小系统图，对于设计CPLD的板子有作用-This is the EPM570 ATLREA a minimum of 144 pin CPLD system diagram, for the design of the board has the role of CPLD
superkeyboard
- 简易电子琴，可以实现弹奏和演奏的双重功能-music player
FPGAdesignandFIRimplementation
- 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
shuziluji
- 纯VHDL文件 拥有闹铃 整点报时 日历 使用方法（打开文件shizhong.gdf文件编译即可（本人使用maxplus-Pure VHDL files have calendar alarm whole hour to use (you can open the file shizhong.gdf file compilation (I use maxplus))
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
PWMcore
- 基于xilinx FPGA软核microblaze编写的PWM波产生IP核，在EXCD开发板上调试通过，内附UCF文件和说明-it s an IP core based on microblaze,it can produce pwm wave.