资源列表
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
ug331
- fpga最全的资料接收，为fpga的入门打下基础 有关的xinlinx的所有的型号-fpga most complete information received, the entry for the fpga xinlinx lay the foundation for all the models
manchester
- verilog 实现manchester编解码，最高速率5mhz-verilog manchester code to achieve the highest rate of 5mhz
FPGAmotor
- FPGA在直流电机调速中的应用,利用fpga进行PID闭环控制-tell us speed control for DC motor by FPGA,use fpga for PID circle control
i2c_verilog_fanli
- i2c程序verilog范例,注释非常详细-i2c program sample verilog
verilogqdpsk
- verilog通信系统设计 verilog通信系统设计-verilog
zx
- CCD图像的颜色插值算法研究及其FPGA实现 ，这是一篇论文，里面详细介绍了如何实现图像处理的方法-CCD color image interpolation algorithm and its FPGA implementation, which is a paper, which details how to implement image processing method
AD_sample_100Mhz
- 用Verilog编写的FPGA AD采样 用Verilog编写的FPGA AD采样-AD_sample_100Mhz
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
uart_16550
- 一个简单的UART源代码，速率可以上到115200，具体看参考时钟-A simple UART source code, the rate can be up to 115200, see the specific reference clock
dcfifo_design_example
- ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助-ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners
adda
- TLC549进行模数转换后在通过tlc5615数模转换出来！结果下载证明可用-TLC549 analog to digital conversion digital-analog conversion through tlc5615 out! The results prove that is available to download