资源列表
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
ultrasonic
- 此源程序代码为基于ＶＨＤＬ语言的超声波检测的软件代码-This source code for VHDL-based ultrasonic testing of software code
DAC8812
- DA转换，Verilog HDL 编的，可实现DA转化。DA芯片用的是DAC8812，实现16位数模转化。-DA conversion, Verilog HDL code, the DA conversion can be achieved. DA-chip using a DAC8812, 16-bit analog-to achieve transformation.
Verilog_IIC
- 利用EP2C8Q208的FPGA芯片，利用Verilog硬件描述语言，实现对AT24C02的EEPROM进行读写操作。-The use of EP2C8Q208 FPGA chip, using the Verilog hardware descr iption language, the realization the AT24C02 of the EEPROM read and write operations.
costas
- 载波同步，costas环，基于Verilog的载波同步环-Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
ls12_mux16
- 一个16位乘法器的veriolog语言实现。使用初学着。-A 16-bit multiplier veriolog language. Use a novice.
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
dds
- 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
8051core-Verilog
- 8051的verilog内核，fpga里实现8051的话用得上-8051 Verilog cores, fpga achieve useful 8051 words
FIFO
- 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
FPGA3.~(6).SchDoc.Zip
- 一个用于数字解调的应用程序，主要用于数字接收机的应用方面-A demodulator for digital applications, mainly for the application of digital receiver