资源列表
chuanbing
- 自己编写的串并变换的fpga程序，使用verilog语言-I have written FPGA series and transform, the use of Verilog language
32ET_source
- 32时隙的VHDL源代码 在开发E1 2M线路的时候非常有用-32 slot of the VHDL source code in the development of E1 2M lines is very useful when
uart_receiver
- This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
key
- 4*4键盘扫描VHDL程序，程序中有产生键值，值得参考-heguo
35_bit_pack
- hiiiiiSystem will automatically delete the directory of debug and release, so please do not put files on these two directory
calibration
- CS5460校准程序，控制器为C8051F310，SPI通信协议，可以作为电表芯片示例-CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample
cntrlr
- verilog code for bus controller
ccd_timing
- tcd1209d drive-timing
FPGA_SPI_Trans
- FPGA模拟SPI与MSP430通讯Verilog程序-A verilog program of fpga talks to mcu msp430 using spi
ads7809
- VHDL model file for Analog devices Analog to Digital converter model ADC7809.
msk
- msk调制verilog HDL 实现，对学习微电子的人很有帮助-msk modulation verilog HDL to achieve, people very helpful in learning Microelectronics
ZZZZ
- 中国机器人大赛擂台赛设计，主要用于11年的机器人比赛，参考-China robot competition arena design, mainly for11 years of robot competitions, reference