资源列表
Quartus_18.0_破解器_Windows密码12345
- Quartus_18.0_破解器_Windows密码12345(Quartus_18.0_crack_Windows,password:12345)
Fundamentals of digital logic with verilog
- Fundamentals of Digital Logic with Verilog Design
rx_module
- 接收机的顶层模块构建,对需要参考的朋友有一定的帮助(The construction of the top module of the receiver is helpful to friends who need reference.)
shifter
- 基于vivado的Xilinx的FPGA其移位寄存器代码(Xilinx's FPGA shift register code based on vivado)
ADS1256
- ads1256驱动代码，用verilog编写,在quartus上运行成功(ADS1256 driver code, written in Verilog, runs successfully on quartus.)
down_up_dds
- 在Vivado下完成AD输入到下变频的功能，频率可配置，通用化设计。(The function of AD input to down conversion is completed under Vivado, and the frequency is configurable and universal design.)
SPI_UART
- SPI读写AD9361，通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)
128点 基8 FFT
- 使用Verilog语言对128点 基8FFT的实现(Implementation of 128-point basis 8FFT)
flashZ
- FPGA控制m25p16flash芯片读写控制spi协议 可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA Erase Write-Read Function)
AD7760_TEST
- AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明(AD7760 Full Function Support with Additional Instructions)
multiplication
- 在FPGA里面实现了多位乘法器的功能，并用modelsim进行了仿真，还对该乘法器进行了优化(The function of multi-bit multiplier is realized in the FPGA, and it is simulated with modelsim, and the multiplier is optimized)
数字信号处理的FPGA实现(第4版)源码
- 数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)