资源列表
数字锁相环设计源程序
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input freque
标准SDR SDRAM控制器参考设计_verilog_lattice
- 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
quartus II中文用户教程(英文版的完全翻译）
- quartus II中文用户教程(英文版的完全翻译）,和一切爱好可编程器件的同仁共勉之-Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi
verilog-som
- 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
FreqCounter
- 一个有效位为4位的十进制的数字频率计,VHDL语言编写，已在硬件实验箱上实验通过。-an effective place to four the number of decimal frequency meter, VHDL language, in the box on the experimental hardware experiment.
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- 数字通信同步技术的MATLAB与FPGA实现 Altera Verilog版.pdf(Synchronization technology of digital communication MATLAB FPGA Altera Verilog.pdf)
AXI slave
- AXI slave 完整 verilog代码。测试验证通过。
异步FIFO
- 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
spartan6 ddr3 controler
- xilinx spartan6 ddr3 test demo
ppm编解码器
- 进行ppm编解码的verilog代码，RTL描述(Verilog code for ppm encoding and decoding, RTL descr iption)
xilinx YUV444 转YUV422
- xilinx chroma resampler application