资源列表
crc3321
- CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
parity2258
- 奇偶校验码的VERILOG源码，为MODELSIM下的一个工程。有测试文件。-parity VERILOG source code for MODELSIM of a project. A test document.
EDATOOL
- EDA的工具介紹(WORD檔)<沒有解壓縮密碼>-introduced EDA tools (Word stalls) lt; No extract passwords gt;
Full_Adder
- 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
time_display&alarm_clock
- 此为在实验板上通过的时钟闹铃程序，源码分别用ASM和VHDL描叙，但两程序功能不同。-this experiment for the board through the alarm clock procedures were used ASM source VHDL and depicts, but the two procedures different functions.
program_all
- 此文件里为我多年收集的子程序模块源代码，对于初学者很适用。用多种语句描叙，有常用的基本电路模块描叙。-this document for many years I collected subroutine module source code, the application for beginners. Using a variety of statements depicts a common basic circuit module depicts.
I2C_read
- I2C读程序，通过状态机描叙,仿真达到要求-I2C Reading, depicts through the state machine, called Simulation
I2C_write
- I2C写程序，程序设计中使用了状态机，并通过输出给指示灯表明状态。-I2C written procedures, program design using state machine, and through to the output indicator showed the state.
MDLS16265B_driver
- 液晶驱动程序，利用DP-FPGA与精电蓬远液晶MDLS16265B测试通过。-LCD driver, the use of DP - FPGA and Varitronix Peng Yuan LCD MDLS16265B test.
bmpelipse
- 实现矩阵的各种操作，加减乘，下载该类可放面以后的编程。-achieve the matrix operation, modified by downloading such caving face future programming.
CePQ
- 测频器，用VHDL语言编写。新手学习作品，还有好多不完善的地方，全当交流，也希望能下载本站原码学习。-frequency measurement device using VHDL language. Rookie learning works, there are a lot of imperfections, when the whole exchange, and hope they can download the original code study site.
select7
- VHDL七人表决器免费为大家服务-VHDL seven people to vote for you for free!