资源列表
ASYfifo
- 这是FIFO程序，开发工具是ISE或QUartus。-procedures, development tools or QUartus ISE.
cdkz
- vhdl编写的彩灯控制程序，比较简单，仅供初学者参考-vhdl prepared by the Lantern control procedures are relatively simple, reference is for beginners
zlqdq
- vhdl编写的智力抢答器程序，比较简单，仅供参考-vhdl prepared by the intelligence Responder procedure is relatively simple, for information purposes only
led_decode
- 用veilog HDL编的七段译码显示电路。自己做的第一个此类程序，编译仿真通过，感觉不错-veilog HDL series with paragraph 107 of the decoder show circuit. I have done the first such procedure, compile through simulation, feeling good
count_usebasketball
- 一个小程序，用Veilog HDL编写的，可以用于篮球比赛的倒计时牌，已在max-plusII上仿真通过。-a small program, prepared by the Veilog HDL, can be used for the basketball game countdown. have max-plusII on through simulation.
risc_spm
- advanced digital design with the verilog hdl-advanced digital design with the verilog h dl
CSpeed
- 采集电压 用研华6220板卡采集电压值 实时显示 电压变化-Acquisition voltage with Advantech 6220 Card Collecting real-time display voltage voltage changes
byvhdstopwatchl
- 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl la
VHDL_TIMESET
- 本专题之研究，为使用硬件描述语言VHDL规划成自己所需要的硬件控制电路，配合上FPGA可程序化硬件设备中的相关模组，而发展出一套数位电子钟之控制器实现。-study of the topic, for the use of VHDL hardware descr iption language into their planning the necessary hardware control circuit, coupled with FPGA hardware program to the
PUKverilogPPT1-9PAGE
- 我收藏的北京大学的verilog的PPT,希望对大家有用,这是1-9章,随后上传剩下的-collection of the Beijing University verilog the PPT, a member of the useful, which is 1-9 chapter Subsequently the remaining Upload
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Viterbi_v
- Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.