资源列表
SPI
- SPI BUS VHDL实现-VHDL SPI BUS
hamming_decoderhamming_encoder
- hamming_decoder hamming_encoder.rar 希望对大家有帮助-hamming_decoder hamming_encoder.rar hope to be helpful
SPEND
- 硬件出租车记数器完整的VHDL语言设计，可以仿真下载测试-hardware taxi Register complete VHDL design, simulation can be downloaded test
FLOOR1
- 电梯的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-lift the hardware descr iption language design, testing can be downloaded and simulation, through the development of EDA system debugging
CLKGDF
- 电子钏的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-electronic bracelets hardware descr iption language design, testing can be downloaded and simulation, through the development of EDA system debugging
EDATRAFFICVHDLLIGHT
- 交通灯的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-traffic lights at the hardware descr iption language design, testing can be downloaded and simulation, through the development of EDA system debugging
first4
- 4人抢答器的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-four Responder hardware descr iption language design, test and can be downloaded simulation, EDA through the development of system debugging
hdb3_verilog
- modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
fpgadigitalclock
- My thesis entitled \"fpga digital clock,\" immature, to enlighten -My thesis entitled "fpga digital clock, "immature, to enlighten
FPGA_drives_LED
- 本压缩文件包含：使用VHDL来实现对LED的静态显示，实现对LED的动态显示。-the compressed file contains : VHDL use of LED to achieve the static, LED to achieve the dynamic display.
my_design_frequency
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, th
hanmin
- 4位汉明编译码源代码。VHDL格式，经过仿真和测试通过，请放心使用。-four Hamming encryption source code. VHDL format, through simulation and test pass, please rest assured that use.