资源列表
COUNT_10
- VHDL源代码.设计一个带有异步清0功能的十进制计数器。计数器时钟clk上升沿有效，清零端为clrn,进位输出为co。 -VHDL source code. Asynchronous design with a 0-counter function of the metric system. Counter clock clk ascending effective end to reset clrn, rounding output co.
COUNT_4qiduan
- VHDL源代码.设计一个模为4的计数器，并在实验箱上用七段数码管显示结果-VHDL source code. Design a scale of four counters, and the experimental box used in paragraph 107 of Digital Display Results
renyizhengshufenpingdeVHDLdaima
- 本文件是实现任意整数分频的VHDL代码,愿与大家分享!-this document is arbitrary integer frequency VHDL code, and is willing to share with you!
FPGAExpressVHDLReferenceManual
- FPGA Express VHDL Reference Manual,对学习VHDL的人来说很好-Express FPGA VHDL Reference Manual, VHDL to study the good people!
dds-design
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
DSPuva16
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
PCB(Cadence)
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
timers.pspice
- PSpice model for 555 timer
lifang_VHDL
- 该代码是实现函数的立方源代码，用VHDL写的，在软件上已经用过了-code is the function of the cube source code, written in VHDL, the software has been used on the
keyboard4_4
- 该代码是4乘4标准键盘扫描程序的源代码，用VHDL编写的，我在调试的时候忘记设置复位键了，大家也要注意了-The code is 4 x 4 standard keyboard scan a program's source code, prepared by the use of VHDL, I remember when debugging set the reset button, we have to pay attention to the
16b20b
- 16b20b编解码VHDL代码.-16b20b codecs VHDL code.
8bit-cpu-of-mul-and-div
- 包含跳转，乘法，除法8位CPU以及一些基本的逻辑运算功能-includes Jump, multiplication, division eight CPU and some of the basic logic operations