资源列表
jop_core_decode
- JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA
jop_core_core
- JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information
jop_core_arom
- 这是最后一个，处理器内部ROM，如有需要，大家就顶-this is the last one, the processors internal ROM, if necessary, on the top you
fixed_pointDivider
- 本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
FPGA_FIR
- VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
15AlteraSOUNDCODE
- altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER
SS7160.ZIP
- 该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.
DE2
- 辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.
firmatlab
- fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
ddsmatlab
- dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
sinmdlmatlab
- 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
xapp290
- 从Xilinx网站上下的，学习FPGA部分动态重配置很好的例子。-from across the Xilinx website, learning some FPGA dynamic reconfigurable good example.