资源列表
8LEDverilog
- //led.v /*------------------------------------- LED显示模块：led(CLK,AF,ADDR,DATA) 功能： 显示 注意事项： 8位LED 参数： CLK:扫妙时钟输入，推荐1kHz AF:数码管输出，a～h ADDR:数码管选择位数出，0~2 DATA:显示数据输入0~9999 9999 编写人： 黄道斌 编写日期： 2006/07/13 ----------------
24miao
- 24秒倒计时系统（有跑马灯） 利用CPLD-24 seconds remaining systems (5,250) using CPLD
frequency_meter_VHDL
- 一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter
wb_conbus.tar
- wishbone 源代码，opencore-wishbone source code, opencore
jop_rom
- JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
jop_core_bcfetch
- JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis
jop_core_cache
- JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits
jop_core_decode
- JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA
jop_core_core
- JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information
jop_core_arom
- 这是最后一个，处理器内部ROM，如有需要，大家就顶-this is the last one, the processors internal ROM, if necessary, on the top you
fixed_pointDivider
- 本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
FPGA_FIR
- VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding