资源列表
ISE_uart
- 自己在ISE下用VHDL写的UART，简单，易懂-in ISE using VHDL was the UART, simple, understandable
ddr_verilog_xilinx
- 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
VHDL_
- vhdl一些重要的例子 内容很丰富 无解压密码-instantiate some important examples of very rich content without extracting passwords
zldjkzjq
- max+plusII下编成的直流电机控制器vhd-under monument of the DC motor controller vhd
ongame
- 一个游戏 the hardware for the game includes a number of displays, each with a button and -- a light, that each represent a bin that can store marbles (beans). -- -- The display indicates the number of marbles in each bin at any given time. --
csxl
- 相应加法器的测试向量（test bench)-corresponding Adder test vector (test bench )
jfq1
- vhdl和verling hdl 的加法器-VHDL and the Adder.
ztj
- max+plusII下的使用列举类型的状态机-max plusII use of the listed types of state machine.
jcq
- max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
jiaotongdeng
- 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码-a VHDL prepared by the CPLD on the analog signal source code
watch2
- vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
20060412183015974
- 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures