资源列表
csxl
- 相应加法器的测试向量（test bench)-corresponding Adder test vector (test bench )
jfq1
- vhdl和verling hdl 的加法器-VHDL and the Adder.
ztj
- max+plusII下的使用列举类型的状态机-max plusII use of the listed types of state machine.
jcq
- max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
jiaotongdeng
- 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码-a VHDL prepared by the CPLD on the analog signal source code
watch2
- vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
20060412183015974
- 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
traffic_light
- 一个用verilog编写的模拟交通灯控制的源代码。模拟在十字路口的双向交通灯。-a prepared using Verilog simulation of traffic lights to control the source code. Simulation at the crossroads of two-way traffic lights.
sdramusevhdl
- sdram的vhdl实现 本文介绍了sdram的控制时序特征，并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
scu_all_fpga
- 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
addch1
- 用vhdl语言设计CPU中的一部分：加法器的设计，包括多种加法器的设计方法！内容为英文-design using VHDL language part of the CPU : Adder design, Adder including multiple design! As for the English
mul6
- 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English