资源列表
vhdll
- 输入为8421BCD码，输出为8421BCD码。 程序中自动对输入进行转换，将8421BCD转换成余3码，然后采用修正函数实现加法，并且利用程序将加法结果转换成8421BCD码进行输出，且输出转换前后的中间结果。 -8421BCD code input and output for 8421BCD yards. Procedures for automatic input conversion, will be converted into 8421BCD I 3 yards, and
timeconstraint
- VHDL编程中的时序约束问题，有两个PDF文件，讲的很详细，需要的立刻下载-VHDL programming timing constraints, there are two PDF documents, said very detailed, immediately download the
FSKmodemodulateVHDLprogramme
- FSK调制与解调的vhdl源代码与仿真指导，是word文档打开。-FSK modulation and demodulation of VHDL source code and simulation of the guide is the word document open.
FPGAdesignstudy
- 介绍了FPGA设计全流程 和一些简单的例子-introduced FPGA design the whole process and some simple examples
programggvv
- 洗衣机程序-washing machines procedures
xiaoche
- 用VHDL编程的智能寻迹小车.驱动电机沿黑线运动,转弯的时候有灯显示.可以综合,实际硬件调试通过.是学习VHDL的很好实例-VHDL programming smart tracking.The car. Electric drives along the black line campaign turning the lights are shown. can comprehensive, practical hardware debugging through. learning is a
100vhdl_EXAMPLE
- vhdl的100个例子,希望对大家有用-VHDL of 100 examples, we hope to useful
FIR31
- 设计一个线性相位FIR滤波器（31阶） 输入8位，输出8位,H(n)={1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69,111,128,111,……2,1} H(n)具有对称性。 输入信号范围 [±99，0，0，0， ±70，0，0，0， ±99，0，0，0， ±70，…]
adderN
- N位加法器源代码，通用的，通过xilinx验证，希望对大家有用。-N-bit adder source code, a common, through Xilinx certification, useful for all.
Verilog_intr_c1
- verilog设计进阶，提供大量的设计事例供参考学习-Verilog design provides many examples of the design study for reference
pcirtl
- 用verilog编写的pci——rtl级。-using Verilog prepared by the pci -- rtl level.
car_lamp
- 汽车转向灯控制电路,采用循环点亮三个指示灯指出汽车的转弯方向。-vehicle steering control circuit lights, cycle lights that lit three cars turning direction.