资源列表
BBSdfbdgdr
- 如果遇到MD5加密文件，而又不知道密码的， 请在数据库中换上这组加密的数据吧 16位：7a57a5a743894a0e 32位：21232f297a57a5a743894a0e4a801fc3 那么密码就是admin-if they MD5 encryption, and do not know the password. please database with a group of encrypted data it 16 : 7a57a5a743894a0e 32
yyue
- 音乐小程序，初学者使用参考-small procedures, the use of reference beginners
async--RS232
- async--RS232VERILOG HDL原代码-async -- RS232VERILOG HDL source
Quaalu
- ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲-ALU arithmetic logic unit to achieve a simple, using VHDL language, can be additive, subtractive, and the place and move around only one clock pulse
Quaacounterx
- 通过VHDL语言编写的计数器程序,可以在一吗器显示管上分段显示小时,分,秒,并且可以分别清零-VHDL prepared by the Counter procedures, in a yet-tube shown above show hours, and seconds can be reset respectively
d_BCD
- CPLD制作的BCD译码器软件,包含源代码等-CPLD produced by the BCD decoder software, including source code, etc.
shzizhong
- 文件名称：数字钟设计参考文章 文件信息：4个文件/pdf/－页 语言种类：中文 适合对象：新手/中手 -file names : Digital Clock reference design document article : four documents / pdf /-page variety of languages : Chinese suitable targets : novice / Hand
verilog_ise_spatan3_clock
- verilog 时钟程序实例在ise下编译通过spatan3的芯片-Verilog clock procedures and ideally under the examples compiled by the chip spatan3
numberword
- 计数器控制程序，希望能够给大家帮助！文件在ＭＡＸ ＰＬＵＳ下开发，调试通过-counter control procedures, we hope to be able to help! MAX PLUS document under development, through debugging
ref-ualaw
- A率/u率 压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
statem
- 元件例化与层次设计，verilog 实例说明-components cases with the level of design, Verilog example
200512251221612004
- 本文件是altera公司fpga的ip核，从国外网站下载的免费源码。-ALTERA This document is the company they simply ip nuclear, downloaded from the web free source.