资源列表
MDLS16265B_driver
- 液晶驱动程序，利用DP-FPGA与精电蓬远液晶MDLS16265B测试通过。-LCD driver, the use of DP - FPGA and Varitronix Peng Yuan LCD MDLS16265B test.
bmpelipse
- 实现矩阵的各种操作，加减乘，下载该类可放面以后的编程。-achieve the matrix operation, modified by downloading such caving face future programming.
CePQ
- 测频器，用VHDL语言编写。新手学习作品，还有好多不完善的地方，全当交流，也希望能下载本站原码学习。-frequency measurement device using VHDL language. Rookie learning works, there are a lot of imperfections, when the whole exchange, and hope they can download the original code study site.
select7
- VHDL七人表决器免费为大家服务-VHDL seven people to vote for you for free!
verilog_code_673
- 各种基本单元的verilog模块.对初学者很有帮助的.-basic unit of Verilog modules. Helpful for beginners.
adder4_1
- 这是用vhdl编写的四位加法器，请多指教-this is the preparation of the four VHDL Adder, please enlighten
URAT_VHDL
- URAT VHDL程序与仿真 各程序运行环境为MAXPLUS_-UART procedures and VHDL simulation environment for the operation of the procedures for MAXPLUS_
i2cdesign
- 这是我做的I2C的vhdl程序和仿真和下载文件，请指教！！！！1！1-This is what I do I2C procedures and the VHDL simulation and download files, please advise! ! ! ! 1! 1
SEGMENT_SCAN_CLOCK_24
- 設計VHDL24小時的時鐘，去除了按鍵彈跳現象-design VHDL24-hour clock, in addition to keys bouncing phenomenon
vhdl00101
- vhdl源程序，对大家学习VHDL一定会有帮助！-VHDL source code, the right to study VHDL will be helpful!
pwm-20010309[1].tar
- PWM产生程序，绝对经典，好就顶一下先，谢谢了-PWM a process absolute classics, and what good on top first, I thank the
sum99
- 基于maxplus2的八位加法器，已经通过仿真-maxplus2 based on the eight Adder, through simulation