资源列表
freqcntr
- 分频器 几次分频欧次分频 vhdl 语言实现-several hours, frequency dividers Europe subregional frequency VHDL Language
fifo_VHDL
- 该文件是先入先出fifo的源代码和测试文件-the document is first-in-first out fifo the source code and test document
RAM_VHDL
- 该文件时RAM的源文件和测试文件以及仿真文件-the document RAM source document and test papers and documents Simulation
i2c_control
- 本文件是iic总线控制器的vhdl语言的源代码程序-2005/09 Bus Controller VHDL language source code procedures
freecore
- 一些vhdl源代码 一些vhdl代码-some VHDL source code for some VHDL source code some VHDL code
state_classic
- 用VHDL语言编写的语言,可以利用MODELSIM进行仿真.对于初学者,则更有参考价值.-prepared using the VHDL language, we can use MODELSIM simulation. For beginners, the more valuable reference.
divded-VHDL
- 一个简单的ＶＨＤＬ分频模块，可以嵌套自己的子程序实现任意分频-a simple VHDL-frequency module, which can be nested subroutine achieve their arbitrary frequency -
CK20-VHDL
- 经典ＣＫ２０时钟程序，实现了时钟的时，分，秒记数，并可以重调，置０-classic procedures CK20 clock and realized the clock, minute and second count, and can be re-emphasize that the Home 0
verilog1
- verilog具体讲解-Verilog
jiaotd
- AD0809的源程序，能使EDA工具箱显示AD0809，具备树模转换功能-AD0809 a source, EDA can show AD0809 a toolbox, with tree-analog converter function
adder16bit
- 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行
VSR4_3
- 甚短距离互联（Veryshort reach VSR）协议编成实现-very short distance from the Internet (Veryshort reach VSR) composition to achieve agreement